1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology and, more particularly, to electrotreating techniques such as electroplating and electroetching that are applied to the entire face of a workpiece.
2. Background of the Related Art
Conventional semiconductor devices such as integrated circuits generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide, and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The interconnects are usually formed by filling a conductor such as copper in features or cavities etched into the dielectric interlayers by a metallization process. The preferred method of copper metallization process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using features such as vias or contacts.
In a typical interconnect fabrication process, first an insulating layer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches, pads and vias etc. in the insulating layer. Then, copper is electroplated to fill all the features. In such electroplating processes the wafer is placed on a wafer carrier and a cathodic (−) voltage with respect to an electrode is applied to the wafer surface while the electrolyte wets both the wafer surface and the electrode. The voltage is typically applied using contacts surrounding the circumference of the wafer. The contacts are usually electrically sealed and isolated from the electrolyte by a clamp covering the circumference of the wafer surface. The clamp inhibits copper deposition on the contacts but it also inhibit copper deposition along the circumference of the wafer and causes loss of important space on the wafer. In the semiconductor industry, this unused or wasted wafer area is called edge exclusion. In the semiconductor integrated circuit industry, there is always a drive towards reducing edge exclusion on the wafers.
Once the plating is over, a chemical mechanical polishing (CMP) step, an electroetching (or electropolishing) or etching step, or a combination of these steps are conducted to remove the excess copper layer or copper overburden and other conductive layers that are above the top surface of the substrate. This process electrically isolates the copper deposited into various features on the wafer and thus forms the interconnect structure. The interconnect process is then repeated as many times as the number of interconnect layers desired.
In the electroetching process both the material to be removed and a conductive electrode are dipped into the electropolishing or electroetching solution. Typically an anodic (positive) voltage is applied to the material to be removed with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface.
Whether a CMP process, an etching process or an electroetching process is employed, it is desirable to reduce the copper overburden thickness that needs to be removed by these processes. The importance of overcoming the copper overburden problem is evidenced by technological developments directed to the deposition of planar and thin copper layers on the wafer surfaces. Such planar deposition techniques are generally called Electrochemical Mechanical Deposition (ECMD). In such planar processes, a pad, a mask or a sweeper, which is collectively called a Workpiece Surface Influencing Device (WSID), can be used during at least a portion of the electrodeposition or electroetching processes when there is physical contact or close proximity, and relative motion between the workpiece surface and the WSID.
The edge exclusion problem may be overcome using deposition technologies that deposit materials across the full face of wafers. For example, U.S. application Ser. No. 09/735,546, entitled “Method and Apparatus For Making Electrical Contact To Wafer Surface for Full-Face Electroplating or Electropolishing,” filed on Dec. 14, 2000 and commonly owned by the assignee of the present invention, now U.S. Pat. No. 6.482,307, describes in one aspect a technique for providing full face electrotreating. It should be noted that electrotreating refers to all electrochemical processes, which are sometimes called by different names. Therefore, electrotreating includes, for example, electrodeposition or plating, electroetching or electropolishing, etc. U.S. application Ser. No. 09/760,757, entitled “Method and Apparatus for Electrodeposition of Uniform Film with Minimal Edge Exclusion on Substrate,” filed on Jan. 17, 2001 and commonly owned by the assignee of the present invention, now U.S. Pat. No. 6,610,757, describes in one aspect a technique for forming conductive layers on a semiconductor wafer surface without losing space on the surface for electrical contacts. As exemplified in these applications, copper deposition or electroetching on a wafer surface can be achieved using electrical contacts to contact the wafer in a slidable manner, i.e., a relative motion is established between the contacts and the wafer surface during process so that material is deposited on or removed from the whole workpiece surface including the areas right under the contacts. While previously described electrical contacts are adequate, needed is an improved contact structure, which provides for even greater consistency than the established electrical contacts.